Integrated semiconductor circuit has n-type independent resistance layer and p-type resistance layer, between which PN junction is formed during reverse bias condition

摘要

An n-type independent resistance layer (4N) is formed in preset area of substrate. A p-type resistance layer (6) is formed in preset area of the layer (4N). A n+ type wall layer (7) surrounds sides of the layer (4N). Impurity concentration of the wall layer is higher than that of layer (4N). Voltage (Vcc) is supplied to the wall layer and PN junction is formed between the layers (4N,6) during reverse bias condition. A power supply is connected with destroyable Zener diode through resistors and the diode is formed on substrate (2). An Independent claim is also included for Zener diode destruction method.