Clock recovery from a burst-mode digital signal each packet of which may have one of several predefined frequencies

摘要

The clock may be recovered rapidly for burst mode signals that are at one of a set of different a priority known frequencies by using a single device that is similar to that of U.S. Pat. No. 5,237,290 except that the delay lines used in each of the gated oscillators are controllably selectable so that the gated oscillators are each capable of providing a clock signal at more than one frequency. Typically, the same frequency is selected for use by both of the gated oscillators at any one time. This is achieved by having each gated oscillator be made up of 1) a plurality of “internal” gated oscillators that each have different length delay lines, and 2) a selector for selecting the output of one of the internal gated oscillators that is to be used for a particular frequency. The internal gated oscillators may be made up of delay elements. The ratio of the number of delay elements in the various internal gated oscillators to each other determines their relative frequency. When the delay elements that make up the internal gated oscillators are inverters, a phase splitter may be employed to insure that the number of delay elements effectively remains odd to insure that oscillation takes place even when a ratio of two in the frequencies recovered is required.