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On-chip cache file register for minimizing CPU idle cycles during cache refills
On-chip cache file register for minimizing CPU idle cycles during cache refills
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机译:片上高速缓存文件寄存器,用于最大程度地减少高速缓存重新填充期间的CPU空闲周期
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摘要
A CPU has an execution unit for operating on data under instruction control. A cache and a buffer register are coupled in parallel to an input of the execution unit. The buffer register supplies an information item, such as data or an instruction, to the execution unit upon the cache having completed a refill process.
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