METHOD OF TROUBLE ANALYSIS USING LOGIC CIRCUIT DIAGRAM AND LAYOUT DIAGRAM COMPOSED OF ONLY NET LIST OF TROUBLE- TRANSMISSION ESTIMATED ROUTE IN SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a display method of data for analyzing the cause of an error generated in a logic circuit which can grasp the connectional relation in a logic circuit easily in a short time when a trouble analysis of a semiconductor integrated circuit is executed.;SOLUTION: The conventional problems are resolved by the following methods: a method of displaying a layout which is linked with the net list provided with the prospected values and estimated values by using the net list of the semiconductor integrated circuit, a list of names of trouble prospect nets, and the prospected value of each net at a test vector for inspecting troubles; and a method of displaying the logic circuit by using only the net list of the trouble prospects.;COPYRIGHT: (C)2002,JPO