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Method for making deep trench capacitors for DRAMs with reduced faceting at the substrate edge and providing a more uniform pad Si3N4layer across the substrate
Method for making deep trench capacitors for DRAMs with reduced faceting at the substrate edge and providing a more uniform pad Si3N4layer across the substrate
A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad silicon nitride (Si3N4) uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.
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机译:实现了一种用于制造用于DRAM电路的改进的深沟槽电容器的方法,该沟槽电容器在晶片边缘处具有减少的沟槽刻面并且具有用于增加工艺的改进的焊盘氮化硅(Si 3 Sub> N 4 Sub>)均匀性产量。该方法利用较厚的Si 3 Sub> N 4 Sub>垫作为用于刻蚀深沟槽的硬掩模的一部分。然后,在通过一系列工艺步骤形成深沟槽电容器之后,形成浅沟槽隔离(STI)。该方法利用在相同的较厚的焊盘Si 3 Sub> N 4 Sub>层中将浅沟槽刻蚀到硅衬底中。沉积第二绝缘层并将其抛光回(CMP)到焊盘Si 3 Sub> N 4 Sub>层中。一个关键特征是使用第二个掩模来保护衬底中心,同时部分地腐蚀由衬底固有产生的衬底边缘处的焊盘Si 3 Sub> N 4 Sub>的较厚部分。 CMP。这样可以最小化焊盘Si 3 Sub> N 4 Sub>的不均匀性,从而为进一步处理提供更可靠的结构。
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