Methods and systems for intelligent I/O controller with channel expandability via master/slave configuration

摘要

An intelligent host adapter for coupling a host PC to peripheral I/O devices through I/O channels wherein the host adapter has a master/slave architecture. A master I/O processor includes circuits for coupling the host adapter to a slot in an I/O interface bus of the host PC such as a PCI bus. The master I/O processor also includes circuits for a relatively small fixed number of I/O channels for connection to associated I/O peripheral busses such as SCSI, Fiber Channel and networks (i.e., Ethernet, token ring, etc.). A slave I/O processor is coupled to the master I/O processor via a dedicated master/slave interface bus. The slave I/O processor provides for addition of I/O channels to the host adapter without requiring use of additional slots of the I/O interface bus of the host PC and without using associated I/O computing resources within the host PC. The slave I/O processor is a simplified version of the master I/O processor in that it is substantially devoid of circuits for interfacing to the host PC I/O interface bus and largely devoid of general purpose processing power as is typical in the master I/O processor. Rather, all access by the host PC to the additional I/O channels of the slave I/O processor is through the master I/O processor and the associated master/slave interface bus. Further all general purpose processing of I/O requests in the host adapter is performed within the general purpose processor of the master I/O processor since the slave I/O processor is substantially devoid of such processing power. This host adapter master/slave architecture permits simpler, more flexible scaling of the number of I/O channels provided by the host adapter without requiring additional use of host PC I/O interface bus slots and associated computing resources.