Formal logic verification system and method

摘要

There is described a means of shortening of the time required for verification by a formal logic verification system which compares details of a circuit represented in the form of a register transfer level (RTL) description with details of the circuit represented in the form of a gate level netlist. Logical equivalence between an RTL description and a gate level netlist obtained through logical compilation of the RTL descriptions is verified. In a case where a plurality of blocks having the same function are included in the circuit, one of a plurality of descriptions that are included in the netlist and relate to the function is compared with the RTL description relating to the functional blocks (comparison {circle around (1)}). If one of the descriptions of the netlist has already been verified, a plurality of descriptions included in the netlist are compared with the description that is taken as the first reference description.