Low power pipelined multiply/accumulator with modified booth's recoder

摘要

A low power high speed multiply/accumulator (100) utilizes a modified Booth's recoder (120) to identify situations to power down the partial product array (130). The modified Booth's recoder (120) is responsive to a NOP signal (116) and a add/subtract signal (118) that result from instruction decode. The partial product array (130) can be partially or fully shut-down to conserve power in response to the recoder (120) detecting certain operands and NOP instructions. It also allows implementation a multiply-and-subtract instruction. The output of the partial product array (130) is registered in a high order product register (142) and a low order product register (144). The low order product register (144) accumulates partial products for multiply-and-accumulate and multiply-and-subtract instructions. The carry bit of the low order product register (144) is added (146) to the high order product register (142) to generate the high order result (152), while the low order result (154) are derived from the low order product register (144).