MEMORY DEVICE WITH REDUNDANCY EVALUATION CIRCUIT AND EVALUATION METHOD FOR REDUNDANCY ADDRESS

摘要

The present invention relates to relates to a memory device having a redundancy function assessment, and a redundancy method pyeonggahoe capable of reducing the power consumption due to the increase of the memory size.; The invention generates a power-up signal during initialization, and to the evaluation node, free the charge and generate a free the charge signal period, and the start signal input in the event of a power-up signal, the evaluation operation is completed for generating a reset signal after the control circuit; Pre-decoding an external address signal applied from the outside when the input of the start signal, and the pre-decoder circuit which is initialized by the reset signal from said control circuit; Is initialized by the power-up signal from the control circuit, a pre-evaluation node by the charge signal is charge-free car in the redundancy address pyeonggahoe for determining the application of pre-decoded address signals applied from the pre-decoder circuit redundancy address and a.