Pointer Adjustment Interval Prediction Circuit for Bit Leaking of Synchronous Digital Threshold

摘要

The present invention relates to the improvement of the jitter characteristic in the synchronous digital hierarchy (SDH) of a broadband transmission system, and more particularly to a circuit for predicting a pointer adjustment period for bit leaking (bit leaking). The present invention gives a constant weight to the number of frames between pointer adjustment intervals generated in the past, and predicts the next pointer generation time while exponentially decreasing from the most recent past value. The present invention uses a single counter and a few calculators, so that the values of the past have a certain weight on the predicted value, thereby preventing a sudden change in the predicted value and significantly reducing the jitter characteristic.