Self-synchronous FIFO memory device having high access efficiency, and system provided with interface for data transfer using the same

摘要

An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in response to the external write request/read request. A next-state function is provided, which has a function to calculate a write address/read address to be input to the RAM in response to the external write request/read request, and a function to accurately count data stored in a FIFO.