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Charge pump circuit with voltage multiplier for boosting clock signal and method thereof
Charge pump circuit with voltage multiplier for boosting clock signal and method thereof
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机译:具有升压时钟信号的倍压器的电荷泵电路及其方法
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摘要
A charge pump circuit is provided. The charge pump circuit includes at least one voltage-boosting stage connected in series with each other and having a supply terminal, a control terminal, and an output terminal respectively, and at least one voltage multiplier having an input terminal, a first output terminal for outputting a first clock signal, and a second output terminal for outputting a second clock signal respectively, wherein the input terminal of a first voltage multiplier is coupled to a clock signal, the first clock signal is a voltage-multiplying signal of the second clock signal, each of the voltage multipliers is coupled the respective second output terminal thereof to the input terminal of a downstream voltage multiplier, and the first output terminal of the voltage multiplier is coupled to the control terminal of a respective one of the voltage-boosting stage.
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