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Compatible effective addressing with a dynamically reconfigurable data space word width
Compatible effective addressing with a dynamically reconfigurable data space word width
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机译:具有动态可重新配置的数据空间字宽的兼容有效寻址
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摘要
A processor has a native word width of multiples of a byte width. The processor may, nonetheless, process, store and retrieve data in word or byte widths depending on the mode of an instruction directing the processing. Instructions may assume either a word or a byte mode. In the word mode, the instruction causes the processor to read, store and operate on word width data. In the byte mode, the instruction causes the processor to read, store and operate on byte data where the byte is specified based on upper/lower byte bits in the instruction. This architecture permits a new generation of processor having word widths of more than one byte to be backward compatible with software written for byte width processors.
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