Process, apparatus and program for transforming program language description of an IC to an RTL description

摘要

An RTL description, such as a Verilog description, of an integrated circuit is derived from a C/C description by defining the integrated circuit as a generalized multiplexer having outputs and two groups of input variables X₁, X₂, . . . , X_s and Y₁, Y₂, . . . , Y_n in which each variable X₁, X₂, . . . , X_s, is fixed and no output depends on more than one variable of Y₁, Y₂, . . . , Y_n. An output vector is constructed by Exclusive-OR operations to find an index j for UU1(BIT(0,j), BIT(1,j), . . . , BIT(K1),j)). The Verilog description of the circuit is a function of the solution of the output vector, or a constant.