Semiconductor memory chip e.g. double data rate SDRAM chip, assesses operating state of memory chip based on phase difference between reference clock signal and delayed operating clock signal

摘要

A phase detector (4) ascertains the phase difference between a reference clock signal and the delayed operating clock signal. A digital counter (5) increments or reduces the count value by '1', when the operating clock signal leads or lags the reference signal, respectively. An evaluation circuit (7) assesses the operating state of the memory chip based on the counter reading. An Independent claim is also included for semiconductor memory chip operating detection method.