RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED RESISTOR SET

摘要

PPROBLEM TO BE SOLVED: To operate a large-scale context switch by using a minimum quantity of overheads. PSOLUTION: An RISC (Reduced Instruction Set Computer) microprocessor architecture is provided with banks, each has a plurality of same-type resistor sets, for a data processor operated in a plurality of modes. A data processor controls access to eliminate the need for specifying any of the given banks through a command and a process. An integer register set includes a first subset, a second subset, and a shadow subset. The command accesses the first and the second sub-sets while the data processor is in a first mode. The command accesses the first subset while the data processor is in a second mode. However, when the command attempts to access the second subset, the command is directed to the shadow sub-set. A user routine saves data written on the second sub-set to seemingly use the second sub-set without reconstitution. PCOPYRIGHT: (C)2004,JPO&NCIPI