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Formation manner of the hetero epitaxial semiconductor substrate, chemical compound semiconductor equipment, and its production manner null which possess this hetero epitaxial semiconductor

机译:拥有该异质外延半导体的异质外延半导体衬底的形成方式,化合物半导体设备及其制造方式无效

摘要

PROBLEM TO BE SOLVED: To manufacture heteroepitaxial substrate making firm sheet resistance and a compound semiconductor device formed on this substrate by raising the set up temperature on said substrate per respective depositions when the first, second and third III-V group semiconductor layers are successively deposited. ;SOLUTION: Within this heteroepitaxial substrate, the first AlGaAs layer 22a, the second AlGaAs layer 22b and a GaAs layer 22c are deposited respectively at 300-400°C on an Si substrate 22 prebaked in hydrogen, at 500-600°C on the first AlGaAs layer 22a and at 650-750°C on the second AlGaAs layer 22b. In such a composition, by the application of the substrate in low oxygen induction laminated layer density i.e., having excellent crystallinity, the diffusion of V group element having the crystallkine defect on the Si substrate 22 can be suppressed thereby enabling the sheet resistance lessening to be avoided.;COPYRIGHT: (C)1997,JPO
机译:解决的问题:当依次沉积第一,第二和第三III-V族半导体层时,通过分别提高每次沉积在所述基板上的设定温度,来制造具有牢固的薄层电阻的异质外延基板以及在该基板上形成的化合物半导体器件。 。溶液:在该异质外延衬底中,第一AlGaAs层22a,第二AlGaAs层22b和GaAs层22c分别在300-400℃下,在氢气中预烘烤的Si衬底22上,在500-600℃下沉积在300-400℃下。第一AlGaAs层22a并在650-750℃下在第二AlGaAs层22b上。在这样的组成中,通过以低的氧感应层压层密度即具有优异的结晶性来施加基板,可以抑制具有晶格缺陷的V族元素在Si基板22上的扩散,从而可以减小薄层电阻。避免。;版权:(C)1997,日本特许厅

著录项

  • 公开/公告号JP3487393B2

    专利类型

  • 公开/公告日2004-01-19

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP19960013355

  • 发明设计人 恵下 隆;宮垣 真治;

    申请日1996-01-29

  • 分类号H01L21/205;C30B29/40;H01L21/20;H01L21/225;H01L21/324;

  • 国家 JP

  • 入库时间 2022-08-21 23:24:16

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