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VLSI chip test power reduction

机译:VLSI芯片测试功耗降低

摘要

LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.
机译:LBIST和加权LBIST测试是在被测对象的不同部分上同时执行的。这种新的测试方法和设计变更实现了与传统测试策略相同的测试覆盖范围和测试时间,并且在测试过程中功耗大大降低。它可以应用于晶圆,芯片,MCM和系统测试级别。最重要的是,它不需要新的支持工具。当前的测试软件将与传统测试策略一样工作。在同一测试会话中安排LBIST和加权LBIST测试的时间可以降低总体功耗,因为加权LBIST测试比平LBIST测试的功耗要少得多。在同一测试会话中,如果逻辑的某些部分使用加权LBIST进行测试,而其他部分使用LBIST进行测试,则电路元件在任何给定时间所消耗的功率都会减少。

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