首页> 外国专利> Efficient cache organization for way-associativity and high refill and copy-back bandwidth

Efficient cache organization for way-associativity and high refill and copy-back bandwidth

机译:高效的缓存组织,实现了路径关联性以及高的重新填充和回写带宽

摘要

In a cache memory access operation data words are retrieved from the cache memory in dependence upon whether the data word reside in the cache memory. If the words reside in cache memory they are provided from the cache memory to a processor, if not then they are brought into cache memory from a main memory. Unfortunately, the data words are stored in cache memory in such a manner that accessing of the cache memory multiple times is required in order to retrieve a single cache line. During the retrieval of the single cache line, the cache memory cannot be accessed for other operations such as cache line refill and copy-back. This results in the processor to incur stall cycles while waiting for these operations to complete. By storing the cache line in such a manner that it spans multiple memory circuits, the processing stall cycles are decreased since fewer clock cycles are required to retrieve the entire cache line from the cache memory. Therefore, more clock cycles are available to facilitate cache line refill and copy-back operations.
机译:在高速缓冲存储器访问操作中,取决于数据字是否驻留在高速缓冲存储器中,从高速缓冲存储器检索数据字。如果字驻留在高速缓存存储器中,则将它们从高速缓存存储器提供给处理器,如果不是,则将它们从主存储器带入高速缓存存储器。不幸的是,数据字以这样的方式存储在高速缓冲存储器中,即,需要多次访问高速缓冲存储器以便检索单个高速缓存行。在检索单个高速缓存行期间,无法访问高速缓存存储器进行其他操作,例如高速缓存行重新填充和回写。这导致处理器在等待这些操作完成时招致停顿周期。通过以跨越多个存储电路的方式存储高速缓存线,减少了处理停顿周期,因为需要更少的时钟周期来从高速缓存存储器检索整个高速缓存线。因此,可以使用更多的时钟周期来促进高速缓存行的重新填充和回写操作。

著录项

  • 公开/公告号US2004030835A1

    专利类型

  • 公开/公告日2004-02-12

    原文格式PDF

  • 申请/专利权人 VAN DE WAERDT JAN-WILLEM;

    申请/专利号US20020218080

  • 发明设计人 JAN-WILLEM VAN DE WAERDT;

    申请日2002-08-12

  • 分类号G06F12/00;

  • 国家 US

  • 入库时间 2022-08-21 23:16:40

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