PHASE COMPARATOR WHICH IS APPLIED TO DELAY LOCKED LOOP CIRCUIT USES CLOCK SIGNAL GENERATED BY RISING AGE AND AS FALLING AGE

摘要

PURPOSE: A phase comparator applied to a delay locked loop circuit is provided to rapidly lock the initial phase since the variable delay line to control the shift register is controlled by using the rising clock signal as well as the falling clock signal. CONSTITUTION: A phase comparator applied to a delay locked loop circuit includes a phase comparison block(10) and a shift register control block(20). The phase comparison block(10) compares the reference clock signal obtained by dividing the clock signal by the divider with the phase of the feedback clock signal generated by the reference clock signal considering the delay line and the delay time of the inner circuit, wherein the clock signal is obtained by buffering the clock signal inputted from the outside. And, the shift register control block(20) controls the delay controller including the shift register to control the delay time of the delay line by using the data outputted from the phase comparison block(10), the rising clock signal generated by synchronizing with the rising edge of the clock signal inputted from the outside and the falling clock signal generated by synchronizing with the falling edge.