Input delay correction system and method for an a / d - transducer and storage medium

摘要

A clock signal supply unit (12) supplies a clock signal with mutually different phases to each A/D converters (22,24). A FIR filter (30) has delay units that delay digitized signal from the converter, which are multiplied with preset coefficients by multipliers. An adder adds the multiplier outputs which is output alternately with delay digital signal having maximum value before multiplication. An Independent claim is included for delay correction method.