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Current switching type of high-speed logic circuit which generates output pair of differential signals each having accurately matched rise-time and fall-time waveform characteristics

机译:电流切换型高速逻辑电路,可产生差分信号的输出对,每个差分信号的上升时间和下降时间波形特性均精确匹配

摘要

A two-input logic gate circuit suitable for extremely high-speed operation, which operates on two differential signal pairs expressing respective logic inputs, includes a control signal generating circuit which converts the input differential signal pairs to two sets of differential control signal pairs respectively having first and second level ranges, to be supplied to a current switching section. The current switching section includes first and second switching stages each formed of two source-coupled FET pairs, with differential control signal pairs of the first and second level ranges being applied to FET pairs of the first and second switching stages respectively, with the current switching section thereby selectively establishing current paths to generate a differential signal pair at two load resistors such that each signal of that differential pair results from switching of currents flowing in an identical number of paths, and with each path passing via an identical number of FETs into respective current sources, thereby enabling an output differential signal pair to be obtained in which each signal has identical rise-time and fall-time characteristics.
机译:一种适用于极高速操作的两输入逻辑门电路,其对表示各自逻辑输入的两个差分信号对进行操作,包括控制信号生成电路,该电路将输入的差分信号对转换为分别具有以下特性的两组差分控制信号对:第一和第二电平范围,将被提供给电流切换部分。电流开关部分包括第一开关级和第二开关级,每个开关级由两个源极耦合的FET对形成,并且通过电流开关将第一和第二电平范围的差分控制信号对分别施加到第一和第二开关级的FET对。从而有选择地建立电流路径,以在两个负载电阻器处产生差分信号对,从而使该差分对的每个信号均来自于流经相同数量路径的电流的切换,并且每个路径都经过相同数量的FET进入各自电流源,从而能够获得输出差分信号对,其中每个信号具有相同的上升时间和下降时间特性。

著录项

  • 公开/公告号US6911847B2

    专利类型

  • 公开/公告日2005-06-28

    原文格式PDF

  • 申请/专利权人 HIROAKI ASANO;MITSURU SAITO;

    申请/专利号US20010900167

  • 发明设计人 MITSURU SAITO;HIROAKI ASANO;

    申请日2001-07-09

  • 分类号H03K19/094;H03K19/20;

  • 国家 US

  • 入库时间 2022-08-21 22:20:06

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