Instruction cache apparatus and method capable of increasing a instruction hit rate and improving instruction access efficiency

摘要

The present invention provides an instruction cache apparatus and method using the instruction read buffer. The apparatus comprises an instruction hit analysis unit, an instruction read buffer, a first cache instruction word memory, a second cache instruction word memory, a first multiplexer and a second multiplexer. The instruction hit analysis unit receives a programmable counter output signal, compares this with a plurality of tags, and after the analysis, outputs the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. The second multiplexer reads the expected instruction word from one of either the first cache instruction word memory, the second cache instruction word memory or the first multiplexer according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. While the bus interface waits for the next demanded instruction word to reply to the instruction read buffer, it writes an instruction line into the first or the second cache instruction word memory. Wherein, the instruction line is in the instruction read buffer and includes the previously expected instruction word.