A logic circuit composing apparatus capable of composing a LUT logic circuit having an intermediate output for a multi-output logic function. There are included characteristic function binary decision graph node table storing means (8) for a characteristic function x (X,Y) of a multi-output logic function f(X); LUT storing means (16); shunt eliminating means (11) for dividing a characteristic function binary decision graph into partial graphs (B0,B1) by a division line having a predetermined height (lev) to provide a shunt elimination; BDD width measuring means (12) for measuring the width (W) in the division line; intermediate variable calculating means (13) for calculating, based on the width (W), the number of intermediate variables; LUT generating means (14) for generating LUT for the partial graph (B0); and BDD rearranging means (15) for generating a binary tree having control inputs the number of which is equal to the number (u) of the intermediate variables, and for replacing the partial graph (B0) by the binary tree to rearrange the characteristic function binary decision graph.
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