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ISOLATED HIGH-VOLTAGE LDMOS TRANSISTOR HAVING A SPLIT WELL STRUCTURE
ISOLATED HIGH-VOLTAGE LDMOS TRANSISTOR HAVING A SPLIT WELL STRUCTURE
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机译:具有良好阱结构的隔离式高压LDMOS晶体管
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摘要
The isolated high-voltage LDMOS transistor according to the present invention includes a split N-well and P-well in the extended drain region. The P-well is split in the extended drain region of the N-well to form a split junction-field in the N-well. The split N-well and P-well deplete the drift region, which shifts the electric field maximum into the bulk of the N-well. This achieves a higher breakdown voltage and allows the N-well to have a higher doping density. Furthermore, the LDMOS transistor according to the present invention includes an N-well embedded beneath the source diffusion region. This creates a low-impedance path for the source region, which restricts the transistor current flow between the drain region and the source region.
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