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ISOLATED HIGH-VOLTAGE LDMOS TRANSISTOR HAVING A SPLIT WELL STRUCTURE

机译:具有良好阱结构的隔离式高压LDMOS晶体管

摘要

The isolated high-voltage LDMOS transistor according to the present invention includes a split N-well and P-well in the extended drain region. The P-well is split in the extended drain region of the N-well to form a split junction-field in the N-well. The split N-well and P-well deplete the drift region, which shifts the electric field maximum into the bulk of the N-well. This achieves a higher breakdown voltage and allows the N-well to have a higher doping density. Furthermore, the LDMOS transistor according to the present invention includes an N-well embedded beneath the source diffusion region. This creates a low-impedance path for the source region, which restricts the transistor current flow between the drain region and the source region.
机译:根据本发明的隔离的高压LDMOS晶体管在扩展的漏极区域中包括分离的N阱和P阱。 P阱在N阱的扩展漏极区中分裂,以在N阱中形成分裂结场。分开的N阱和P阱耗尽了漂移区,从而将最大的电场转移到N阱的主体中。这实现了更高的击穿电压,并使N阱具有更高的掺杂密度。此外,根据本发明的LDMOS晶体管包括嵌入在源极扩散区下方的N阱。这为源极区域创建了低阻抗路径,从而限制了晶体管电流在漏极区域和源极区域之间的流动。

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