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Without notch etching of high aspect ratio SOI structures using Yu pulsed plasma etching and deposition and alternating

机译:使用Yu脉冲等离子体蚀刻,沉积和交替进行高深宽比SOI结构的无缺口蚀刻

摘要

According to the present invention, a method for preventing notching during the deposition cycle and etching of the substrate using an inductively coupled plasma source is provided. By this method, the inductively coupled plasma source is generated pulses in order to prevent charge accumulation on the substrate. Off state of an inductively coupled plasma source, is long enough to be able to flow out of the charges are generated, it is selected so that it is not long enough to etch rate is low due to a low duty cycle. Pulse generator may be controlled to occur only when the substrate is etched insulating layer is exposed. Well, the bias voltage may be to generate a pulse in out of phase or in phase with the pulse generation of the inductively coupled plasma source can be applied to the insulating layer a bias voltage.
机译:根据本发明,提供了一种用于防止在沉积循环期间产生切口和使用感应耦合等离子体源蚀刻基板的方法。通过这种方法,感应耦合等离子体源产生脉冲,以防止电荷积聚在基板上。感应耦合等离子体源的截止状态足够长,以能够流出所产生的电荷,因此选择截止状态的时间不长,以至于由于低占空比而导致蚀刻速率低。可以控制脉冲发生器以仅在基板被蚀刻时暴露绝缘层。很好,该偏置电压可以产生异相或与感应耦合等离子体源的脉冲产生同相的脉冲,可以将偏置电压施加到绝缘层。

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