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Being the device which draws up the truth value chart which shows the relationship

机译:是绘制真实值图表以显示关系的设备

摘要

PROBLEM TO BE SOLVED: To efficiently prepare a truth table for a combinational logic circuit. ;SOLUTION: An input signal sequence is prepared (S1) by arranging plural input signal patterns in certain order so that a humming distance can become '1' before and after, and the input signal patterns are successively extracted from the top one by one (S2). As for the first extracted pattern, processing for generating an output signal pattern is performed by propagating the input signal to all the logic gates inside the logic circuit (S4) and concerning the pattern extracted for the (n) time (n1), processing for updating the output signal pattern is performed by specifying one input bit having a logic value different from that of the pattern extracted in (n-1) time and propagating the input signal only through the logic gate affected by this input bit (S5). The respective input signal patterns and the generated or updated output signal patterns are made correspondent so that the truth table can be prepared (S6).;COPYRIGHT: (C)1997,JPO
机译:解决的问题:有效地为组合逻辑电路准备真值表。 ;解决方案:通过按一定顺序排列多个输入信号图样来准备输入信号序列(S1),以使嗡嗡声的距离在前后都变为``1'',然后从顶部开始依次提取输入信号图样( S2)。对于第一提取图案,通过将输入信号传播到逻辑电路(S4)内的所有逻辑门并涉及在(n)次(n> 1)内提取的图案,来执行用于生成输出信号图案的处理。通过指定一个具有与(n-1)次中提取的模式的逻辑值不同的逻辑值的输入位,并且仅通过受该输入位影响的逻辑门传播输入信号,来执行更新输出信号模式的处理(S5) 。使各个输入信号模式与生成或更新的输出信号模式相对应,以便可以准备真值表(S6)。;版权:(C)1997,JPO

著录项

  • 公开/公告号JP3808129B2

    专利类型

  • 公开/公告日2006-08-09

    原文格式PDF

  • 申请/专利权人 大日本印刷株式会社;

    申请/专利号JP19960088832

  • 发明设计人 酒井 秀樹;

    申请日1996-03-18

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 21:49:37

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