A switch driver circuit, for driving a switching circuit, comprises a data node for receiving an input data signal (TODD), a clock node for receiving a clock signal (CLKODD), first and second output nodes for supplying drive signals (VS1 and VS2) to the switching circuit, a first switch (SW8) for connecting the clock node to the first output node, and a second switch (SW7) for connecting the clock node to the second output node. The circuit is arranged such that the first and second switches do not change state when a clock signal received at the clock node changes state. Two or more such switch driver circuits, supplied with separate clock signals and data signals, may be used to supply drive signals to a common differential switching circuit, for example in a digital-to-converter.
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