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Circuit arrangement for clocked integration e.g. for digital signal processing, uses pattern recognition logic for ascertaining first and second locations of law-non-law and non-law-law transitions
Circuit arrangement for clocked integration e.g. for digital signal processing, uses pattern recognition logic for ascertaining first and second locations of law-non-law and non-law-law transitions
A circuit arrangement (1) for clocked integration uses K clocked flip-flop devices (2-1...2-K) for temporary storage of the K bits, and pattern recognition logic (3) for determining a first location of a law-non-law transition and a second location for a non-law-law transition in the temporarily stored integration result and for output of both ascertained locations through a first thermometer-coded transition display signal (T1).
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