Programmable gain amplifier with reduced gain switching transients

摘要

A programmable gain amplifier (PGA) 10 (fig.8) includes combined high pass filter and attenuator circuits 30, 32 and 35 (fig.8). Each filter attenuator circuit comprises capacitors 58, 59 in series with signal input lines Iin, IBin, and a chain of resistors 61 - 64 between the lines. A plurality of switches are formed by PMOS / NMOS transistor pairs 65/66 - 71/72. In use, the outer pair of MOS switches (65/66, 71/72) are on (closed) and the inner pair (67/68, 69/70) are off (open), or, the inner pair are closed and the outer pair are open. To reduce the magnitude of switching transients, glitches or noise that can appear on the signal lines Iout, IBout when the MOS switch control lines sg1 - sg4 are operated (due, for example, to parasitic capacitances), the timing of the control signals on lines sg1 - sg4 is arranged (fig.7) so that there is a period tc during which both the inner and the outer MOS switches are closed. As an alternative, also disclosed is the use of a 'slow switch' waveform (fig. 10b) which has a slow rising edge and a slow falling edge. This signal may be applied to all the MOS switch control lines sg1 - sg4 simultaneously. The PGA finds application in amplification stages following frequency conversion in wireless communication receivers, e.g. for receiving a CDMA signal. Reduced circuit area and power consumption are disclosed.