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Timing-driven synthesis with area trade-off

机译:时序驱动的综合与区域权衡

摘要

An embodiment of the invention is a logic minimization method that provides improved user design performance without a substantial increase in user design area. Alternate factorizations are determined for portions of the user design. For each factorization, a delay metric is computed. The user design is optimized by selecting factorizations based on a balance of performance and area considerations. The optimized design is then mapped to the hardware architecture of the programmable device. A first portion of the user design is mapped to maximize performance, while a second portion of the user design is mapped to minimize area. The first portion of the user design includes a set of data paths each having a delay metric above a delay threshold. The delay metric can be derived from a unit delay computation or from timing analysis.
机译:本发明的实施例是一种逻辑最小化方法,其提供了改进的用户设计性能,而没有显着增加用户设计面积。为用户设计的各个部分确定替代分解。对于每个分解,都会计算一个延迟度量。通过基于性能和面积考虑的平衡选择因式分解来优化用户设计。然后将优化的设计映射到可编程设备的硬件体系结构。用户设计的第一部分被映射为最大化性能,而用户设计的第二部分被映射为最小面积。用户设计的第一部分包括一组数据路径,每个数据路径都具有高于延迟阈值的延迟度量。延迟度量可以从单位延迟计算或时序分析中得出。

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