Apparatus and method for reducing delay in operating time caused during DRAM hidden refresh operation

摘要

An arrangement for reducing delay in an operating time of a memory device caused during a DRAM hidden refresh operation, includes a memory bank having memory cells, first and second data buses connected to the memory bank, a cache memory connected to the second data bus, and a latch connected to the second data bus. In response to a memory write command, the second data bus transmits data read from the cache memory to the latch in an i^th period of time (i is a natural number), and the data read from the latch to the memory bank in an (i+1)^th period of time. In response to a cache write command, the second data bus transmits data read from the memory bank to the latch in an i^th period of time, and the data read from the latch to the cache memory in an (i+1)^th period of time.