Clock signal generator and phase and delay locked loop comprising the same

摘要

Clock generation circuit and method of generating clock signals. The clock generation circuit includes an inverter directly receiving an external clock signal and outputting an inverted external clock signal, M (where M is an integer =1) loop circuits arranged in series, the first loop circuit receiving the inverted external clock signal, each of the N loop circuits having n (where n is an integer =2) nodes, each of the M-1 loop circuits generating n intermediate internal clock signals, each at a corresponding one of the n nodes, wherein a frequency of the n intermediate internal clock signals is a multiple of a frequency of the external clock signal and the inverted external clock signal; and n sets of inverters, each including M-1 inverters connected in series, each of the M-1 inverters receiving a corresponding intermediate internal clock signal from a previous loop circuit and outputting a corresponding intermediate internal clock signal to a next loop circuit.