Page buffer for non-volatile memory device, e.g. flash memory, has shared sense circuit that joins latch input node to reference potential in response to voltages at sense node and at other cache latch node

摘要

Page buffers blocks (PBB) have sense nodes connected to the bitlines (BLm) of a memory cell array (MCARR). A switching circuit connects the cache latch node of a cache latch circuit to a latch input node that is connected to the main latch nodes of a main latch circuit. A shared sense circuit joins the latch input node to a reference potential in response to voltages at the sense node of the page buffer block and at the other cache latch node of the cache latch circuit. Independent claims are also included for the following: (1) a non-volatile memory device; and (2) a method of operating non-volatile memory device.