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INSPECTION DEVICE, FAILURE ANALYSIS SYSTEM, AND FAILURE ANALYSIS METHOD

机译:检查装置,故障分析系统和故障分析方法

摘要

PROBLEM TO BE SOLVED: To provide a failure analysis method capable of reducing an inspection cost and also improving the failure analyzing accuracy.;SOLUTION: An electrical performance test is carried out for memory cells of a semiconductor storage device having a plurality of blocks which include first to n-th wordlines (n is integer≥4) and a plurality of memory cells arranged on intersections between the first to n-th wordlines and a plurality of bit lines, and the test results about the n-2 pieces of memory cells corresponding to 2 to (n-1)th wordlines on the same bit line are condensed to m pieces (m is integer satisfying 1≤m≤n-3), and a condensed fail bit map is developed, of which the test results corresponding to the first wordline and the n-th wordline and the test results of condensed m pieces are mapped, then, failure modes generated in the semiconductor storage device are classified in accordance with the number of pieces of defective bit appeared in the condensed fail bit map, the shapes and the appeared places.;COPYRIGHT: (C)2009,JPO&INPIT
机译:解决的问题:提供一种能够降低检查成本并提高故障分析精度的故障分析方法;解决方案:对具有多个块的半导体存储器件的存储单元进行电性能测试,包括第一至第n字线(n为整数4)和多个存储单元布置在第一至第n字线与多条位线之间的相交处,并且关于n-2个存储单元的测试结果将与同一位线上的第2至第(n-1)个字线对应的m压缩为m个片段(m为满足1≤ n-3的整数),并生成一个压缩的失效位图,其测试结果对应映射到第一字线和第n字线并映射压缩的m个测试结果,然后,根据压缩的f中出现的缺陷位的数量对在半导体存储器件中产生的故障模式进行分类所有位图,形状和出现的位置。;版权所有:(C)2009,JPO&INPIT

著录项

  • 公开/公告号JP2009140601A

    专利类型

  • 公开/公告日2009-06-25

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;

    申请/专利号JP20070318690

  • 发明设计人 IIZUKA YOSHIKAZU;

    申请日2007-12-10

  • 分类号G11C29/40;G01R31/28;

  • 国家 JP

  • 入库时间 2022-08-21 19:44:18

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