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Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device

机译:电路合用范式生成方法,电路合用范式生成装置,危害检查方法及危害检查装置

摘要

A hazard check method and device for making hazard checks of logic circuits containing asynchronous paths and multi-cycle paths. The hazard check device includes a means for equivalent conversion to only pre-embedded conjunctive normal form blocks if not all of the blocks in the logic circuit were embedded conjunctive normal form blocks; a means for tracing each termination point recorded in the signal information from the logic circuit, inputting the signal information to the circuit up to the flip-flop, and assigning numerals to each net; and a means for tracing each termination point recorded in the signal information from the logic circuit, referring to the logic library for each block, and searching for the same logic conjunctive normal form (CNF) as in the logic library, and substituting the conjunctive normal form into the numerals assigned to the connected network, and outputting it as the circuit conjunctive normal form; and a means for adding a circuit conjunctive normal form whose logic is equivalent to that numeral, to each net for each termination point recorded in the signal information.
机译:一种用于对包含异步路径和多循环路径的逻辑电路进行危害检查的危害检查方法和装置。危险检查装置包括一种装置,如果逻辑电路中不是所有的块都不是嵌入的普通正态形式块,则仅等价转换为预嵌入的普通正态块;跟踪来自逻辑电路的信号信息中记录的每个终止点,将信号信息输入到直到触发器的电路中,并给每个网络分配数字的装置;跟踪来自逻辑电路的信号信息中记录的每个终止点的方法,该方法参考每个块的逻辑库,并搜索与逻辑库中相同的逻辑结范式(CNF),并替换结范式形成分配给所连接网络的数字,并将其输出为电路联合范式;对于在信号信息中记录的每个终止点的每个网络,将逻辑等效于该数字的电路联合范式添加到该网络。

著录项

  • 公开/公告号US7617466B2

    专利类型

  • 公开/公告日2009-11-10

    原文格式PDF

  • 申请/专利权人 KO YOSHIKAWA;

    申请/专利号US20060586516

  • 发明设计人 KO YOSHIKAWA;

    申请日2006-10-26

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 19:30:20

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