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Methods and cores using existing PLD processors to emulate processors having different instruction sets and bus protocols
Methods and cores using existing PLD processors to emulate processors having different instruction sets and bus protocols
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机译:使用现有PLD处理器来模拟具有不同指令集和总线协议的处理器的方法和内核
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摘要
Methods and cores using an existing processor implemented in a Programmable Logic Device (PLD) to emulate a target processor, where the existing and target processors support different instruction sets and conform to different bus interface protocols. A bus interface unit is coupled to an existing processor in a PLD. The bus interface unit is implemented using the programmable logic resources of the PLD, while the existing processor can be a dedicated processor or an existing “soft” processor. The bus interface unit acts as a peripheral device to translate bus transactions from the existing bus protocol (i.e., the bus protocol understood by the existing processor) to the target bus protocol. In addition, a stored emulation program emulates the target instruction set while executing instructions using the instruction set supported by the existing processor.
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