首页> 外国专利> MULTIPLE-CHANNEL SELF-ALIGNMENT TRANSISTOR FABRICATED BY DOUBLE SELF-ALIGNMENT PROCESS AND ITS MANUFACTURING METHOD

MULTIPLE-CHANNEL SELF-ALIGNMENT TRANSISTOR FABRICATED BY DOUBLE SELF-ALIGNMENT PROCESS AND ITS MANUFACTURING METHOD

机译:双重自对准过程制造的多通道自对准晶体管及其制造方法

摘要

A multiple-channel self-alignment transistor fabricated through double self-alignment process by sequentially determining the positions of the gate, drain, and source electrodes by two back exposures, having a vertical structure using a comb gate electrode, and having multiple short channels and its manufacturing method are provided. A multiple-channel self-alignment transistor fabricated by a double self-alignment process comprises opaque gate electrodes (11) of a comb shape formed on a substrate (10), an insulating film (21) formed over the opaque gate electrodes (11), a transparent drain electrode (12) formed by a first back exposure through the substrate (10) between the comb opaque gate electrodes (11), transparent source electrodes (13) formed above an insulating film (21a) formed thereon and the comb opaque gate electrodes (11) by a second back exposure through the substrate (10), and a semiconductor (31) formed thereon.
机译:一种通过双自对准工艺制造的多通道自对准晶体管,该工艺是通过两次背曝光顺序确定栅极,漏极和源极的位置,并具有使用梳状栅电极的垂直结构,并具有多个短沟道和提供了其制造方法。通过双重自对准工艺制造的多沟道自对准晶体管包括:梳状的不透明栅电极(11),其形成在基板(10)上;绝缘膜(21),形成在不透明栅电极(11)上。透明漏电极(12)是通过在不透明梳状栅电极(11)之间通过基板(10)进行第一次背曝光而形成的,透明源电极(13)形成在其上形成的绝缘膜(21a)上方并且不透明梳状栅电极(11)通过衬底(10)进行第二次背曝光,并在其上形成半导体(31)。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号