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SAMPLE AND HOLD INTEGRATED CIRCUIT, METHOD FOR COMPENSATION LEAKAGE IN SAMPLE AND HOLD CIRCUIT, AND SAMPLING CIRCUIT USED IN INTEGRATED CIRCUIT
SAMPLE AND HOLD INTEGRATED CIRCUIT, METHOD FOR COMPENSATION LEAKAGE IN SAMPLE AND HOLD CIRCUIT, AND SAMPLING CIRCUIT USED IN INTEGRATED CIRCUIT
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机译:样品和保持集成电路,样品和保持电路中的补偿泄漏的方法以及在集成电路中使用的采样电路
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摘要
PROBLEM TO BE SOLVED: To provide a method and an apparatus for holding a sampled value for a long time on a capacitor and substantially reducing the effects of switch leakage current with respect to the stored value.;SOLUTION: A sample and hold circuit in one aspect includes first and second switches. The first switch can be coupled to receive an input signal and to sample the input signal using a first capacitor. A first leakage current flows between first and second conductive terminals of the first switch and accumulates as a first leakage charge in the first capacitor. A second leakage current flows between the first and second conductive terminals of the second switch and accumulates as a second leakage charge in the second capacitor. An offset circuit produces a compensated sampled value by subtracting a quantity from a signal developed in response to the held sampled signal and charge accumulated through the first switch, wherein the quantity is developed in response to the accumulated leakage charge in the second capacitor.;COPYRIGHT: (C)2010,JPO&INPIT
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