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Phase dithered digital communications system
Phase dithered digital communications system
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机译:相位抖动数字通信系统
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摘要
The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.
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