Dual-port SRAM memory using a single-port memory cell

摘要

Run the dual port function using the [problem] single-port cell, to eliminate the intermittent data Tsu only to minimize the cell layout area by it. Dual-port memory cell is implemented using [SOLUTION] single-port memory cells. In order to synchronize and prioritize access request associated with the two ports, the access arbiter comprising a synchronization circuit is used. Access arbiter, may be when the single-port memory cells require refresh to synchronize and prioritize the refresh request. The refresh request and the access request on the two ports, and can be a asynchronous. Latched in the register of the first stage the request when the row access signal (RAS) is activated, the access arbiter, the second-stage register the contents of the first register stage after a delay after which the selected by latching within, to synchronize the various requirements. [Selection] Figure Figure 1