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Production manner, plasma etching manner and plasma etching device of semiconductor equipment

机译:半导体设备的生产方式,等离子体蚀刻方式及等离子体蚀刻装置

摘要

The present invention provides a method for manufacturing a semiconductor device. In the method, a connection hole such as a via hole is formed in an interlayer insulating film by plasma etching with high etching uniformity regardless of the array density of connection holes. In the method, an upper layer film having a mask pattern is formed on the interlayer insulating film present on a substrate. A gas required for dehydration is then supplied to the substrate under the condition that an upper surface of the interlayer insulating film is exposed in order to remove moisture from the interlayer insulating film. A portion of the interlayer insulating film is etched to form a connection hole in which an electrical connection portion is to be embedded.
机译:本发明提供一种用于制造半导体器件的方法。在该方法中,与连接孔的排列密度无关,通过具有高蚀刻均匀性的等离子体蚀刻在层间绝缘膜中形成诸如通孔的连接孔。在该方法中,在基板上存在的层间绝缘膜上形成具有掩模图案的上层膜。然后,在露出层间绝缘膜的上表面的条件下,将脱水所需的气体供给至基板,以从层间绝缘膜去除水分。蚀刻层间绝缘膜的一部分以形成其中将嵌入电连接部的连接孔。

著录项

  • 公开/公告号JP5272336B2

    专利类型

  • 公开/公告日2013-08-28

    原文格式PDF

  • 申请/专利权人 東京エレクトロン株式会社;

    申请/专利号JP20070164170

  • 发明设计人 千葉 祐毅;田原 慈;

    申请日2007-06-21

  • 分类号H01L21/3065;H01L21/768;

  • 国家 JP

  • 入库时间 2022-08-21 16:56:46

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