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Reconfigurable microprocessor configured with multiple caches and configured with persistent finite state machines from pre-compiled machine code instruction sequences
Reconfigurable microprocessor configured with multiple caches and configured with persistent finite state machines from pre-compiled machine code instruction sequences
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机译:可重配置的微处理器,配置有多个缓存,并配置有来自预编译的机器代码指令序列的持久性有限状态机
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摘要
A processor, integrated with re-configurable logic and memory elements, is disclosed which is to be used as part of a shared memory, multiprocessor computer system. The invention utilizes the re-configurable elements to construct persistent finite state machines based on information decoded by the invention from sequences of CISC or RISC type processor machine instructions residing in memory. The invention implements the same algorithm represented by the sequence of encoded instructions, but executes the algorithm consuming significantly fewer clock cycles than would be consumed by the processor originally targeted to execute the sequence of encoded instructions.
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