首页> 外国专利> On-chip test technique for low drop-out regulators, comprising finite state machine

On-chip test technique for low drop-out regulators, comprising finite state machine

机译:低压降稳压器的片上测试技术,包括有限状态机

摘要

A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.
机译:描述了一种用于自动测试集成电路芯片上的多个LDO稳压器电路的电路和方法,该电路和方法独立于ATE。每个LDO稳压器都经过测试以指定的电流输出能力进行电压测试,其中输出驱动器晶体管由至少两个传输晶体管形成,每个传输晶体管都经过测试以特定的电流能力进行电压输出。测试结果将返回到ATE,如果测试失败,则可以通过模拟多路复用器观察通过设备的栅极电压,以启用调试功能。

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