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Method and apparatus for minimizing cache conflict misses

机译:用于最小化高速缓存冲突未命中的方法和装置

摘要

A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided. The translation table includes multiple entries, and each entry of the translation table includes a page number field and a hash value field. A hash value is generated from a first group of bits within a virtual address, and the hash value is stored in the hash value field of an entry within the translation table. In response to a match on the entry within the translation table during a cache access, the hash value of the matched entry is retrieved from the translation table, and the hash value is concatenated with a second group of bits within the virtual address to form a set of indexing bits to index into a cache set.
机译:公开了一种用于最小化高速缓存冲突未命中的方法。提供了一种转换表,其能够在高速缓存访​​问期间促进虚拟地址到真实地址的转换。转换表包括多个条目,并且转换表的每个条目包括页码字段和哈希值字段。从虚拟地址内的第一组位生成哈希值,并将该哈希值存储在转换表内条目的哈希值字段中。在高速缓存访​​问期间,响应于翻译表中条目的匹配,从翻译表中检索匹配条目的哈希值,并将该哈希值与虚拟地址内的第二组位连接起来,以形成一个一组索引位以索引到高速缓存集。

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