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Delay-locked loop arrangement and method for operating a delay-locked loop circuit
Delay-locked loop arrangement and method for operating a delay-locked loop circuit
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机译:延迟锁定回路装置和操作延迟锁定回路电路的方法
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摘要
Delay-locked loop arrangement comprising a steering unit (STR) and a delay-locked loop circuit (DLL). The steering unit (STR) is configured to generate a reference clock signal (S_rclk) and a main clock signal (S_mclk) wherein the reference clock signal (S_rclk) and the main clock signal (S_mclk) feature a first frequency during a performance mode of operation. The reference clock signal (S_rclk) and the main clock signal (S_mclk) feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation. The delay-locked loop circuit (DLL) is configured to generate an error signal (S_err) depending on a comparison of the reference clock signal (S_rclk) and a feedback signal (S_fb). Furthermore, the delay-locked loop circuit (DLL) generates the feedback signal (S_fb) depending on the error signal (S_err) and on the main clock signal (S mclk).
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