Aspects disclosed in the detailed description include optimizing interconnect designs in low-power integrated circuits (ICs). In this regard, in one aspect, functional blocks having substantially correlated power utilization patterns are grouped into a power-related cluster to share a sleeping cell, thus leading to a reduced number of sleep transistors and a simplified interconnect design in a low-power IC. In another aspect, functional blocks having higher block temperatures are separated into more than one power-related cluster, improving heat dissipation in the low-power IC. A simulated annealing (SA) process is employed to determine an optimized placement for the low-power IC based on a power-related cost function that includes a power-related parameter and a heat-related parameter. By running the SA process based on the power-related cost function, it is possible to determine the optimized placement that leads to the reduced number of sleep transistors and improved heat dissipation in the low-power IC.
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