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Network-on-chip architecture for multi-processor SoC designs
Network-on-chip architecture for multi-processor SoC designs
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机译:多处理器SoC设计的片上网络架构
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摘要
A system and method embodying some aspects for communicating between nodes in a network-on-chip are provided. The system comprises a microprocessing chip and a plurality of connection paths. The microprocessing chip comprises sixteen processing nodes disposed on the chip. The plurality of connection paths are configured such that each is at most three hops away from any other node. Each node also has connection paths to at most three other nodes.
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