MAPPING BETWEEN REGISTERS USED BY MULTIPLE INSTRUCTION SETS

摘要

A PROCESSOR (4) IS PROVIDED WHICH SUPPORT A FIRST INSTRUCTION SET (24) SPECIFYING 32-BIT ARCHITECTURAL REGISTERS (8) AND A SECOND INSTRUCTION SET (26) SPECIFYING 64-BIT (8) REGISTERS (8). EACH OF THESE INSTRUCTION SETS IS PRESENTED WITH ITS OWN SET OF REGISTERS (8) FOR USE. THE FIRST SET OF REGISTERS (8) PRESENTED TO THE FIRST INSTRUCTION SET (24) HAS A ONE-TO-ONE MAPPING TO THE SECOND SET OF REGISTERS (8) PRESENTED TO THIS SECOND INSTRUCTION SET (26). THE REGISTERS (8) WHICH ARE PROVIDED IN HARDWARE ARE 64-BIT REGISTERS. IN SOME EMBODIMENTS, WHEN EXECUTING PROGRAM INSTRUCTIONS OF THE FIRST INSTRUCTION SET (24) ONLY THE LEAST SIGNIFICANT PORTION OF THESE 64-BIT REGISTERS (8) ARE ACCESSED AND MANIPULATED WITH THE REMAINING MOST SIGNIFICANT PORTION OF THE REGISTERS (8) BEING LEFT UNALTERED. REGISTER SPECIFYING FIELDS WITHIN INSTRUCTIONS OF THE FIRST INSTRUCTION SET (24) ARE DECODED TOGETHER WITH A CURRENT EXCEPTION MODE TO DETERMINE WHICH REGISTER TO USE WHERE AS THE SECOND INSTRUCTION SET (26) USES REGISTER SPECIFYING FIELDS WITHOUT A DEPENDENCE UPON EXCEPTION MODE TO DETERMINE WHICH REGISTER ARE TO BE USED. FIGURE 9