首页> 外国专利> How to optimize and reduce cycle times for integrated circuits, package design and verification

How to optimize and reduce cycle times for integrated circuits, package design and verification

机译:如何优化和减少集成电路,封装设计和验证的周期时间

摘要

A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements.
机译:一种制造集成电路产品的方法和由此形成的集成电路产品。该方法包括设计具有多个IC连接组的IC封装,每个IC连接组被配置为连接到从具有不同功能的多个IC中选择的对应IC。可以根据选择的IC连接到其对应的连接组来生产各种IC产品,并且可以在设计过程中切割IC封装以排除与未选择的IC相对应的IC连接组。通过测试完整的IC封装,可以从完整的IC封装中切出完整IC封装的一部分,从而大大降低了设计和测试要求。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号