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How to optimize and reduce cycle times for integrated circuits, package design and verification
How to optimize and reduce cycle times for integrated circuits, package design and verification
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机译:如何优化和减少集成电路,封装设计和验证的周期时间
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摘要
A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements.
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